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 HD74LVC2G66
2-channel Analog Switch
REJ03D0024-0300 Rev.3.00 Jul.07.2005
Description
The HD74LVC2G66 has 2-channel analog switch in an 8-pin package. Each switch section has its own enable input control (CONT). High-level voltage applied to CONT turns on associated switch section. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
* * * * * The basic gate function is lined up as renesas uni logic series. Supply voltage range: 1.65 to 5.5 V Operating temperature range: -40 to +85C Control inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Ordering Information
Part Name HD74LVC2G66CPE WCSP-8 pin HD74LVC2G66CLE Package Type Package Code (Previous Code) SXBG0008KA-A (TBS-8V) SXBG0008KB-A (TBS-8AV) CP E (3,000 pcs/reel) CL Package Abbreviation Taping Abbreviation (Quantity)
Article Indication
Marking Year code Month code
E66YM
Function Table
Control L H H : High level L : Low level Switch OFF ON
Rev.3.00 Jul 07, 2005 page 1 of 11
HD74LVC2G66
Pin Arrangement
0.9 mm Height 0.5 mm 0.5 mm pitch 0.17 mm 8-Ball (CP) 0.23 mm 8-Ball (CL)
GND
4
5
IN/OUT2
CONT2
3
6
OUT/IN2
OUT/IN1
2
7
CONT1
1.9 mm
Pin#1 INDEX
IN/OUT1
1
8
VCC
(Bottom view)
(Top view)
Logic Diagram
IN/OUT1 CONT1
OUT/IN1
one of two switches
Absolute Maximum Ratings
Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Package Thermal impedance Storage temperature Notes: Symbol VCC VI VO IIK IOK IO ICC or IGND ja Tstg Ratings -0.5 to 6.5 -0.5 to 6.5 -0.5 to VCC +0.5 -50 -50 50 100 140 102 -65 to 150 Unit V V V mA mA mA mA C/W C Test Conditions
Output : H or L VI < 0 VO < 0 VO = 0 to VCC
CP CL
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum.
Rev.3.00 Jul 07, 2005 page 2 of 11
HD74LVC2G66
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Input transition rise or fall rate Symbol VCC VI VO t / v Min 1.65 0 0 0 Max 5.5 5.5 VCC 20 10 10 85 Unit V V V ns / V Conditions
0 0 Operating free-air temperature Ta -40 Note: Unused or floating inputs must be held high or low.
VCC = 1.65 to 1.95 V, 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
C
Rev.3.00 Jul 07, 2005 page 3 of 11
HD74LVC2G66
Electrical Characteristics
* Ta = -40 to 85C
Item Input voltage Symbol VIH VCC (V) 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 VIL 1.65 to 1.95 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 On-state switch resistance RON 1.65 2.3 3.0 4.5 Peak on resistance RON(P) 1.65 2.3 3.0 4.5 Difference of on-state resistance between switches RON 1.65 2.3 3.0 4.5 Off-state switch leakage current On-state switch leakage current Control input current Quiescent supply current Control input capacitance Switch terminal capacitance Note: 1. Ta = 25C IS (OFF) 5.5 Min VCCx0.65 VCCx0.7 VCCx0.7 VCCx0.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IS (ON) IIN ICC ICC CIC CI/O(OFF) CI/O(ON) 5.5 5.5 5.5 5.5 5.0 5.0 5.0 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- 12.5 9 7.5 6 85 22 12 7.5 -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 6.0 14.0 Max -- -- -- -- VCCx0.35 VCCx0.3 VCCx0.3 VCCx0.3 30 20 15 10 120 30 20 15 7 5 3 2 1.0 0.1*1 1.0 0.1* 1.0 0.1* 10 1.0* -- -- --
1 1 1
Unit V
Test condition
IS = 4 mA IS = 8 mA IS = 24 mA IS = 32 mA IS = 4 mA IS = 8 mA IS = 24 mA IS = 32 mA IS = 4 mA IS = 8 mA IS = 24 mA IS = 32 mA
VI=VCC to GND VI=VCC to GND VI=VCC or GND
A
VI = VCC and VO = GND or VI = GND and VO = VCC, VC = VIL VI = VCC or GND, VC = VIH VO = Open VIN = VCC or GND VIN = VCC or GND VC = VCC-0.6 V
A A A A pF pF
500
Rev.3.00 Jul 07, 2005 page 4 of 11
HD74LVC2G66
Switching Characteristics
* VCC = 1.8 0.15 V
Item Propagation delay time*1 Enable time Disable time Symbol tPLH, tPHL tZH, tZL tHZ, tLZ Ta = -40 to 85C Min Max 2.0 2.3 2.5 10.0 10.5 Unit ns Test Conditions CL = 30 pF, RL = 1.0 k CL = 30 pF, RL = 1.0 k CL = 30 pF, RL = 1.0 k FROM (Input) INOUT or OUTIN CONT CONT TO (Output) OUTIN or INOUT INOUT or OUTIN INOUT or OUTIN
* VCC = 2.5 0.2 V
Item Propagation delay time*1 Enable time Disable time Symbol tPLH, tPHL tZH, tZL tHZ, tLZ Ta = -40 to 85C Min Max 1.2 1.6 1.2 5.6 6.9 Unit ns Test Conditions CL = 30 pF, RL = 500 CL = 30 pF, RL = 500 CL = 30 pF, RL = 500 FROM (Input) INOUT or OUTIN CONT CONT TO (Output) OUTIN or INOUT INOUT or OUTIN INOUT or OUTIN
* VCC = 3.3 0.3 V
Item Propagation delay time*1 Enable time Disable time Symbol tPLH, tPHL tZH, tZL tHZ, tLZ Ta = -40 to 85C Min Max 0.8 1.5 2.0 4.4 7.2 Unit ns Test Conditions CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 CL = 50 pF, RL = 500 FROM (Input) INOUT or OUTIN CONT CONT TO (Output) OUTIN or INOUT INOUT or OUTIN INOUT or OUTIN
* VCC = 5.0 0.5 V
TO (Output) OUTIN or INOUT Enable time tZH, tZL 1.3 3.9 CL = 50 pF, RL = 500 INOUT or OUTIN Disable time tHZ, tLZ 1.1 6.3 CL = 50 pF, RL = 500 CONT INOUT or OUTIN Notes: 1. The propagation delay is calculated RC time const constant of typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Item Propagation delay time*1 Symbol tPLH, tPHL Ta = -40 to 85C Min Max 0.6 Unit ns Test Conditions CL = 50 pF, RL = 500 FROM (Input) INOUT or OUTIN CONT
Rev.3.00 Jul 07, 2005 page 5 of 11
HD74LVC2G66
Analog Switch Characteristics
Ta = 25C Item Frequency response (Switch ON)
VCC (V)
1.65 2.3 3.0 4.5 1.65 2.3 3.0 4.5 1.65 Crosstalk (between switches) 2.3 3.0 4.5 1.65 2.3 3.0 4.5 1.65 Crosstalk (Control input to signal 2.3 output) 3.0 4.5 1.65 Feed through attenuation 2.3 (Switch OFF) 3.0 4.5 1.65 2.3 3.0 4.5 Sine-wave distortion 1.65 2.3 3.0 4.5 1.65 2.3 3.0 4.5
Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ 35 120 175 195 >300 >300 >300 >300 -58 -58 -58 -58 -42 -42 -42 -42 35 50 70 100 -58 -58 -58 -58 -42 -42 -42 -42 0.1 0.025 0.015 0.01 0.15 0.025 0.015 0.01
Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Unit
Test conditions
FROM (Input)
TO (Output) OUTIN or INOUT
MHz CL = 50 pF, Adjust fin voltage to INOUT or RL = 600 obtain 0dBm at output OUTIN when fin is 1MHz (sine wave). CL = 5 pF, Increase fin frequency until the dB-meter RL = 50 reads -3 dBm. 20 log(VO/VI)= -3 dBm dB CL = 50 pF, Adjust fin voltage to INOUT or OUTIN RL = 600 obtain 0dBm at input when fin is 1MHz (sine wave). CL = 5 pF, RL = 50
OUTIN or INOUT
mV
CL = 50 pF, Adjust RL value to RL = 600 obtain 0A at IIN/OUT when fin is 1MHz (square wave) CL = 50 pF, Adjust fin voltage to RL = 600 obtain 0dBm at input when fin is 1MHz (sine-wave) CL = 5 pF, RL = 50
CONT
OUTIN or INOUT
dB
INOUT or OUTIN
OUTIN or INOUT
%
CL = 50 pF, RL = 10 k fin = 1kHz (sine-wave) CL = 50 pF, RL = 10 k fin = 10kHz (sine-wave)
VI=1.4VP-P, VCC=1.65V VI=2.0VP-P, VCC=2.3V VI=2.5VP-P, VCC=3.0V VI=4.0VP-P, VCC=4.5V
INOUT or OUTIN
OUTIN or INOUT
Operating Characteristics
Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 Min -- -- -- -- Typ 8 9 9.5 11 Max -- -- -- -- Unit pF Test Conditions f = 10 MHz
Rev.3.00 Jul 07, 2005 page 6 of 11
HD74LVC2G66
Test Circuit
* RON
VCC VC =VIH VCC VIN =VCC (ON) GND VOUT R ON =
VIN-OUT IS
()
+
IS
-
V
VIN-OUT
* I S (off), I S (on)
VCC VC =VIL VCC A VIN =VCC or GND (OFF) GND VOUT =GND or VCC VIN =VCC or GND A VC =VIH VCC (ON) GND VOUT OPEN VCC
Rev.3.00 Jul 07, 2005 page 7 of 11
HD74LVC2G66
Test Circuit (cont.)
VTT RL S1 OPEN CL Load circuit INPUTS VCC (V) 1.80.15 2.50.2 3.30.3 5.00.5 VI VCC VCC VCC VCC tr / tf 2 ns 2 ns 2.5 ns 2.5 ns Vref VCC / 2 VCC / 2 VCC / 2 VCC / 2 VTT 2 x VCC 2 x VCC 2 x VCC 2 x VCC CL 30 pF 30 pF 50 pF 50 pF RL 1.0 k 500 500 500 RL GND TEST t PLH / tPHL t ZH / t HZ t ZL / t LZ S1 OPEN GND VTT
From Output
V 0.15 V 0.15 V 0.3 V 0.3 V VI
Input
Vref t PLH
Vref t PHL 0V V OH
Output
Vref
Vref V OL VI
Control Input
Vref t ZL
Vref t LZ 0V VOH
Output (Waveform - A)
Vref VOL + V t ZH t HZ VOH - V V OL V OH
Output (Waveform - B)
Vref VOL
Notes: 1. CL includes probe and jig capacitance. 2. Waveform-A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform-B is for an output with internal conditions such that the output is high except when disabled by the output control. 4. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50 . 5. The output are measured one at a time with one transition per measurement.
Rev.3.00 Jul 07, 2005 page 8 of 11
HD74LVC2G66
Frequency response (Switch ON) VCC VC = V IH f in = sine wave f in 0.1 F VIN RL = 50 VCC (ON) GND RL= 600 or 50 VCC /2 VOUT CL = 50 pF or 5 pF
Crosstalk (Between any switches)
VCC VC =VIH 0.1 F RL = 600 or 50 VIN V CC (ON) GND RL = 600 or 50 VCC /2 VCC VC =VIL VCC RL = 600 or 50 VCC /2 (OFF) GND VOUT2 RL = 600 or 50 VCC /2 CL = 50 pF or 5 pF VOUT1 CL = 50 pF or 5 pF
f in RL = 50
Rev.3.00 Jul 07, 2005 page 9 of 11
HD74LVC2G66
Crosstalk (Control input to signal output) VCC RL = 50 VC V CC VOUT RL = 600 VCC /2 Feedthrough attenuation (Switch OFF) V CC VC = VIL 0.1 F RL = 50 VCC /2 Sine-wave distortion V CC VC = VIH 10 F 600 VIN V CC (ON) GND RL = 10 k VCC /2 10 F VIN RL = 600 or 50 V CC (OFF) GND VCC /2 VOUT RL = 600 or 50 CL = 50 pF or 5 pF GND RL = 600 VCC /2 CL = 50 pF
f in
f in
VOUT
CL = 50 pF
Rev.3.00 Jul 07, 2005 page 10 of 11
HD74LVC2G66
Package Dimensions
JEITA Package Code S-XFBGA8-0.9x1.9-0.50 RENESAS Code SXBG0008KA-A Previous Code TBS-8V MASS[Typ.] 0.0014g e D ZD
D
B
C
E
B
A
Reference Symbol
e
ZE
Dimension in Millimeters Min Nom Max 0.50 0.10 0.15 0.35 0.15 0.17 0.90 1.90 0.50 0.05 0.05 0.19
1 Pin#1 index area y1 C A 8 x b
2 A A1 A2 b D E
x M C A B x M C
C Seating plane
e x y y
1
A1
y
C
A2
0.20 0.20 0.20
A
ZD ZE
JEITA Package Code S-XFBGA8-0.9x1.9-0.50
RENESAS Code SXBG0008KB-A
Previous Code TBS-8AV
MASS[Typ.] 0.0015g e
D
ZD
D
B
C
E
B
A
Reference Symbol
e
ZE
Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315) * 0.25 0.90 1.90 0.50 0.05 0.05 0.20 0.20 0.20
1 Pin#1 index area y1 C 8 x b A
2
A A1 A2 b D E 0.20
x M C A B x M C
C Seating plane
e x y y1 Z * Reference value. Z
D E
A1
y
C
A2
Rev.3.00 Jul 07, 2005 page 11 of 11
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's Technology Corp. or a third party. application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas T 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of improvements publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvement or other reasons. It is distributor for the latest product therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distrib information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life ci is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a aerospace, nuclear, or undersea repeater product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. materi 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and lic cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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